1. Field of the Invention
The present invention relates to radio communication systems, and more specifically to a frequency-modulated signal receiver with a digital demodulator.
2. Description of Related Art
The technique of frequency modulation or frequency shift keying is commonly used to transmit a digital signal from a transmitter to a receiver by associating a particular modulation frequency with each digital value of the digital signal. In the case of a binary signal, a frequency f1 is assigned to the value 0 and a frequency f2 to the value 1. The transmitter then has a modulator which, for each digital value, sends the modulation frequency associated with the value and the receiver has a digital demodulator whose task is to restore the binary values of the digital signal by discriminating between the modulation frequencies of the modulated signal that is received.
For example, the demodulation of such signals can consist of measuring the period of the received signal by sampling it at a very high frequency, and comparing the value of the period that is measured with period values corresponding to the different modulation frequencies. The precision of the measurement requires that the frequency of the sampling signal should be far higher than the modulation frequencies of the received signals (i.e., than the frequencies f1 and f2 in the case of a binary signal). The sampling frequency must be made greater as the frequencies f1 and f2 are made higher. The sampling frequency must also be made greater as the frequencies f1 and f2 are made closer to each other so that the demodulator can properly discriminate between them. Thus, in order that the necessary sampling frequency may not be excessively high, the frequency of the received signal is generally lowered to an intermediate frequency of lower value by a frequency-transposition unit placed upline from the digital demodulator in the receiver.
To generate the sampling signal, the receiver usually has a clock circuit assigned exclusively to this use. The presence of such a clock circuit has the following drawbacks: it takes up considerable surface area on the silicon, consumes current, and may also create parasitic noise for the other elements of the receiver.